This invention relates to current mode switched mode power supplies, and circuits for providing fast output current control.
FIG. 1 illustrates a typical prior art current mode switched mode power supply 10 which includes input terminals 12a, 12b for receiving an input voltage waveform V.sub.in (typically a 110 V 60 HZ input voltage) and output terminals 14a, 14b for providing an output current I.sub.0 to a load R.sub.L.
Terminals 12a, 12b are coupled to a rectifying network including a diode bridge 16 and a capacitor 18. A node 20 between diode bridge 16 and capacitor 18 is periodically coupled to a diode 22 and output inductor 24 via a switch 26. When switch 26 is closed, current flows from node 20, through switch 26, inductor 24, and through load R.sub.L. Since current flows through inductor 24, magnetic flux builds up in inductor 24. When switch 26 opens, current is drawn through diode 22 by inductor 24, which in turn flows through load R.sub.L.
Switch 26 is controlled by a latch 30. Latch 30 receives as one input signal a pulse train clock signal CLK FIG. 2a) from a clock circuit 31. On the rising edges 32 of signal CLK, latch 30 is set, and closes switch 26. After switch 26 closes, current I.sub.0 through inductor 24 rises. This current is sensed by a current sense circuit 34, which provides a current sense voltage CSV (FIG. 2b) in response thereto. A comparator 35 compares sense voltage CSV with a control voltage Vc generated by a control voltage generator 36. When voltage CSV exceeds voltage Vc, comparator 35 resets latch 30, thus causing switch 26 to open. In this way, output current through load R.sub.L is regulated to a value dependent on control voltage Vc.
It is frequently necessary to use current mode switched mode power supplies to provide large output currents at high output voltages, e.g., several amperes at 100 to 200 volts. One example of an application of such a current source is for driving a laser tube.
As can be seen in FIG. 2c, output current I.sub.0 has a certain amount of ripple which cannot be eliminated by power supply 10. Also, power supply 10 cannot be regulated to eliminate noise having a frequency greater than that of clock signal CLK, and cannot alter output current I.sub.0 over time periods smaller than several periods of signal CLK. It would be desirable to provide in a current mode switched mode power supply the ability to control output current rapidly, to minimize ripple, and to minimize high frequency noise.